The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device driving current improvement becomes more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance and increasing carrier mobility can improve the device current performance. Gate length reduction is an on-going effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing gate dielectric thickness, increasing gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a strained silicon channel is a known practice. Strain can enhance bulk electron and hole mobility. The performance of a FET device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under strain, the in plane, room temperature electron mobility is dramatically increased. One way to develop strain is using graded SiGe epitaxy layer as substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. FET devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.
Strain can also be applied to the channel region by forming a strain-inducing contact etch stop layer (CESL) over the FET device. When such a contact etch stop layer is deposited, due to the lattice spacing mismatch between the CESL and the underlying layer, an in-plane stress develops to match the lattice spacing. This in-plane strain also results in a Poisson strain perpendicular to the interface.
As shown in FIG. 1, the stress may have components in three directions: parallel to the FET device channel (Δ∈x, or referred as x direction), parallel to the device width (Δ∈y, or referred as y direction), and perpendicular to the channel plane (Δ∈z, or referred as z direction). The stress in the Δ∈x and Δ∈y directions is called in-plane stress. Research has revealed that a CESL that induces a bi-axial in-plane tensile strain field (in both the Δ∈x and Δ∈y direction) can improve NMOS performance. Research has also shown that, for a PMOS device, tensile strain parallel to channel width direction (Δ∈y) also improves POMS device performance, but tensile strain parallel to the channel length (Δ∈x) is detrimental to PMOS device performance.
In order to reduce detrimental effects on a PMOS device, the tensile strain in the Δ∈x direction should be eliminated or reduced, while strain in the Δ∈y direction should be preserved. What is needed in the prior art, then, is a method for improving device performance by promoting desirable strain in a semiconductor layer while minimizing or preventing non-desirable strain, i.e. in a detrimental direction.